This page gives the (current) memory map for Búri. As I add/tweak hardware, this is likely to change. Of course you’re free to re-order I/O as you see fit but this memory map encodes what the Operating System thinks the I/O arrangement is.

Range Description
$0000
$00FF

Zero page.

$D0--$FF are reserved for the OS. The rest is yours.
$0100
$01FF
 Hardware stack page.
$0200
$0205

OS vector table.

Each 2-byte entry gives the little-endian address to jump to for various entry points. The entry points are:

$0200–$0201:Put character (putc)
$0202–$0203:Get character (getc)
$0204–$0205:Is input available? (hasc)
$0206
$02FF
 Operating system reserved RAM space.
$0300
$03FF

Conventional area for RAM-patched OS vectors.

If you patch the OS vector table at $0200 by convention the routines can live in this page. At the moment the OS needs only one page of RAM but this may change in future. You should try and keep the OS vector patches position-independent since it may be neat to add an OS "patch" routine at a later date which chooses where to copy the routine.

$0400
$7FFF

Userspace code RAM area.

Programs are free to use this RAM as they see fit although conventially, code is loaded from address $5000 up and addresses $0400 to $4FFF are used for data storage.

$8000
$DF7F
 Unallocated space.
$DF80
$DF8F
 I/O area 0.
$DF90
$DF9F
 I/O area 1.
$DFA0
$DFAF
 I/O area 2.
$DFB0
$DFBF
 I/O area 3.
$DFC0
$DFCF
 I/O area 4.
$DFD0
$DFDF
 I/O area 5.
$DFE0
$DFEF
 I/O area 6.
$DFF0
$DFFF

I/O area 7.

Within this I/O area, the following hardware registers are assumed to be exposed.

$DFFC:ACIA receive register (read) / transmit register (write)
$DFFD:ACIA status register (read) / programmed reset (write)
$DFFE:ACIA command register
$DFFF:ACIA control register
$E000
$FFF9
 Operating system ROM. (8KB minus processor vectors.)
$FFFA
$FFFB
 Processor jumps to the address stored here on non-maskable interrupt.
$FFFC
$FFFD
 Processor jumps to the address stored here on reset.
$FFFE
$FFFF
 Processor jumps to the address stored here on interrupt when interrupt-disable status flag is clear.